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cy62167gn mobl ? 16-mbit (1m 16/2m 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-93628 rev. *d revised june 23, 2017 16-mbit (1m 16/2m 8) static ram features ultra-low standby power ? typical standby current: 5.5 ? a ? maximum standby current: 16 ? a tsop i package configurable as 1m 16 or 2m 8 sram very high speed: 45 ns temperature ranges ? industrial: ?40 c to +85 c wide voltage range: 1.65 v to 2.2 v, 2.2 v to 3.6 v, and 4.5 v to 5.5 v easy memory expansion with ce 1 , ce 2 , and oe features automatic power-down when deselected cmos for optimum speed and power offered in pb-free 48-ball vfbga and 48-pin tsop i packages functional description the cy62167gn is a high performance cmos static ram organized as 1m words by 16 bits or 2m words by 8 bits. this device features an advanced circui t design that provides an ultra low active current. ultra low active current is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that reduces power consumption by 99 percent when addresses are not toggling. place the device into standby mode when deselected (ce 1 high or ce 2 low or both bhe and ble are high). the input and output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when: the device is deselected (ce 1 high or ce 2 low), outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high), or a write operation is in progress (ce 1 low, ce 2 high and we low). to write to the device, take chip enables (ce 1 low and ce 2 high) and write enable (we ) input low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ) is written into the location spec ified on the address pins (a 0 through a 19 ). if byte high enable (bhe ) is low, then data from the i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 19 ). to read from the device, take chip enables (ce 1 low and ce 2 high) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appears on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see truth table on page 13 for a complete description of read and write modes. 1m 16/2m 8 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 we ble bhe a 16 a 0 a 1 a 17 a 9 a 18 a 10 ce 2 ce 1 a 19 byte power down circuit bhe ble ce 2 ce 1 logic block diagram
document number: 001-93628 rev. *d page 2 of 19 cy62167gn mobl ? contents pin configuration ............................................................. 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 6 thermal resistance .......................................................... 6 ac test loads and waveforms ....................................... 6 data retention characteristics ....................................... 7 data retention waveform ................................................ 7 switching characteristics ................................................ 8 switching waveforms ...................................................... 9 truth table ...................................................................... 13 ordering information ...................................................... 14 ordering code definitions ..... .................................... 14 package diagrams .......................................................... 15 acronyms ........................................................................ 17 document conventions ................................................. 17 units of measure ....................................................... 17 document history page ................................................. 18 sales, solutions, and legal information ...................... 19 worldwide sales and design s upport ......... .............. 19 products .................................................................... 19 psoc? solutions ...................................................... 19 cypress developer community ................................. 19 technical support ................. .................................... 19
document number: 001-93628 rev. *d page 3 of 19 cy62167gn mobl ? pin configuration figure 1. 48-ball vfbga pinout (top view) [1, 2] figure 2. 48-pin tsop i pinout (top view) [2, 3] we a 11 a 10 a 6 a 0 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe vss a 7 i/o 0 bhe ce 2 a 17 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 a 19 a 18 nc 3 2 6 5 4 1 d e b a c f g h a 16 nc v cc a 1 a 2 a 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 a19 nc we ce 2 nc bhe ble a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte vss i/o15/a20 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 vcc i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 oe vss ce 1 a0 product portfolio product range v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( ? a) f = 1 mhz f = f max min typ [4] max typ [4] max typ [4] max typ [4] max cy62167gn18 industrial 1.65 1.8 2.2 55 7 9 29 32 7 26 cy62167gn30 2.2 3.0 3.6 45 29 36 5.5 16 cy62167gn 4.5 5.0 5.5 notes 1. ball h6 for the vfbga package can be used to upgrade to a 32m density. 2. nc pins are not connected on the die. 3. the byte pin in the 48-pin tsop i package has to be tied to v cc to use the device as a 1m 16 sram. the 48-pi n tsop i package can also be used as a 2m 8 sram by tying the byte signal to v ss . in the 2m 8 configuration, pin 45 is a20, while bhe , ble and i/o 8 to i/o 14 pins are not used. 4. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c.
document number: 001-93628 rev. *d page 4 of 19 cy62167gn mobl ? maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ............................... ?65 c to + 150 c ambient temperature with power applied .................................. ?55 c to + 125 c supply voltage to ground potential [5, 6] ................?0.3 v to v cc(max) + 0.3 v dc voltage applied to outputs in high z state [5, 6] ......?0.3 v to v cc(max) + 0.3 v dc input voltage [5, 6] ....................?0.3 v to v cc(max) + 0.3 v output current into outputs (low) ............................. 20 ma static discharge voltage (mil-std-883, method 3015) ................................. >2001 v latch-up current ..................................................... >200 ma operating range device range ambient temperature v cc [7] industrial ?40 c to +85 c 1.65 v to 2.2 v, 2.2 v to 3.6 v, 4.5 v to 5.5 v electrical characteristics over the operating range parameter description test conditions 45 ns/ 55 ns unit min typ [8] max v oh output high voltage 1.65 < v cc < 2.2 i oh = ?0.1 ma 1.4 ? ? v 2.2 < v cc < 2.7 i oh = ?0.1 ma 2.0 ? ? 2.7 < v cc < 3.6 i oh = ?1.0 ma 2.4 ? ? 4.5 < v cc < 5.5 i oh = ?1.0 ma 2.4 ? ? 4.5 < v cc < 5.5 i oh = ?0.1 ma v oh ? 0.5 [9] ?? v ol output low voltage 1.65 < v cc < 2.2 i ol = 0.1 ma ? ? 0.2 v 2.2 < v cc < 2.7 i ol = 0.1 ma ? ? 0.4 2.7 < v cc < 3.6 i ol = 2.1 ma ? ? 0.4 4.5 < v cc < 5.5 i ol = 2.1 ma ? ? 0.4 v ih input high voltage 1.65 < v cc < 2.2 1.4 ? v cc + 0.2 v 2.2 < v cc < 2.7 1.8 ? v cc + 0.3 2.7 < v cc < 3.6 2 ? v cc + 0.3 4.5 < v cc < 5.5 2.2 ? v cc + 0.5 v il input low voltage 1.65 < v cc < 2.2 ?0.2 ? 0.4 v 2.2 < v cc < 2.7 ?0.3 ? 0.6 2.7 < v cc < 3.6 ?0.3 ? 0.8 4.5 < v cc < 5.5 ?0.5 ? 0.8 i ix input leakage current gnd < v i < v cc ?1 ? +1 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ? a i cc v cc operating supply current f = 22.22mhz (45 ns) v cc = v cc(max) i out = 0 ma cmos levels ?2936ma f = 18.18mhz (55 ns) ? 29 32 ma f = 1 mhz ?79ma notes 5. v il(min) = ?2.0 v for pulse durations less than 20 ns. 6. v ih(max) = v cc + 2v for pulse durations less than 20 ns. 7. full device ac operation assumes a 100 ? s ramp time from 0 to v cc(min) and 200 ? s wait time after v cc stabilization. 8. indicates the value for the center of distribution at 3.0 v, 25 c and not 100% tested 9. this parameter is guaranteed by design and not tested.
document number: 001-93628 rev. *d page 5 of 19 cy62167gn mobl ? i sb1 [10] automatic power down current ? cmos inputs ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v, v in < 0.2 v, f = f max (address and data only), f = 0 (oe , and we ), v cc = v cc(max) ?5.516 ? a i sb2 [10] automatic power-down current ? cmos inputs v cc = 2.2 v to 3.6 v and 4.5 v to 5.5 v ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = v cc(max) 25 c [11] ?5.56.5 ? a 40 c [11] ?6.38.0 70 c [11] ? 8.4 12.0 85 c ? 12.0 16.0 automatic power-down current ? cmos inputs v cc = 1.65 v to 2.2 v ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = v cc(max) ? 7.0 26.0 electrical characteristics (continued) over the operating range parameter description test conditions 45 ns/ 55 ns unit min typ [8] max notes 10. chip enables (ce 1 and ce 2 ), byte enables (bhe and ble ) and byte must be tied to cmos levels to meet the i sb1 /i sb2 / i ccdr spec. other inputs can be left floating. 11. indicates the value for the center of distribution at 3.0 v, 25 c and not 100% tested.
document number: 001-93628 rev. *d page 6 of 19 cy62167gn mobl ? capacitance parameter [12] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter [12] description test conditions 48-ball vfbga 48-pin tsop i unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four-layer printed circuit board 31.50 57.99 c/w ? jc thermal resistance (junction to case) 15.75 13.42 c/w ac test loads and waveforms figure 3. ac test loads and waveforms v high v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v th equivalent to: thvenin equivalent all input pulses r th r1 parameters 1.8 v 2.5 v 3.0 v 5.0 v unit r 1 13500 16667 1103 1800 ? r 2 10800 15385 1554 990 ? r th 6000 8000 645 639 ? v th 0.80 1.20 1.75 1.77 v v high 1.8 2.5 3.0 5.0 v note 12. tested initially and after any design or process changes that may affect these parameters.
document number: 001-93628 rev. *d page 7 of 19 cy62167gn mobl ? data retention characteristics over the operating range parameter description conditions min typ [13] max unit v dr v cc for data retention 1.0 ? ? v i ccdr [14, 15] data retention current v cc = 2.2 v to 3.6 v, ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v ?5.516 ? a 1.2 v < v cc < 2.2 v, ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v or (bhe and ble ) > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v ? 7.0 26.0 t cdr [16] chip deselect to data retention time 0??? t r [17, 19] operation recovery time 45/55 ? ? ns data retention waveform figure 4. data retention waveform v cc (min) v cc (min) t cdr v dr > 1.0 v data retention mode t r ce 1 or v cc bhe . ble ce 2 or [18] notes 13. indicates the value for the center of distribution at 3.0 v, 25 c and not 100% tested. 14. chip enables (ce 1 and ce 2 ), byte enables (bhe and ble ) and byte must be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating. 15. i ccdr is guaranteed only after the device is first powered up to v cc(min) and then brought down to v dr . 16. tested initially and after any design or proce ss changes that may affect these parameters. 17. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 ? s or stable at v cc(min) > 100 ? s. 18. bhe .ble is the and of both bhe and ble . deselect the chip by either disabling the chip enable signals or by disabling both bhe and ble . 19. these parameters are guaranteed by design and are not tested.
document number: 001-93628 rev. *d page 8 of 19 cy62167gn mobl ? switching characteristics parameter [20] description 45 ns 55 ns unit min max min max read cycle t rc read cycle time 45.0 ? 55.0 ? ns t aa address to data valid ? 45.0 ? 55.0 ns t oha data hold from address change 10.0 ? 10.0 ? ns t ace ce 1 low and ce 2 high to data valid ? 45.0 ? 55.0 ns t doe oe low to data valid ? 22.0 ? 25.0 ns t lzoe oe low to low z [21, 22] 5.0 ? 5.0 ? ns t hzoe oe high to high z [21, 22, 23] ? 18.0 ? 18.0 ns t lzce ce 1 low and ce 2 high to low z [21, 22] 10.0 ? 10.0 ? ns t hzce ce 1 high and ce 2 low to high z [21, 22, 23] ? 18.0 ? 18.0 ns t pu ce 1 low and ce 2 high to power-up [24] 0 ? 0 ? ns t pd ce 1 high and ce 2 low to power-down [24] ? 45.0 ? 55.0 ns t dbe ble / bhe low to data valid ? 45.0 ? 55.0 ns t lzbe ble / bhe low to low z [21, 22] 5.0 ? 5.0 ? ns t hzbe ble / bhe high to high z [21, 22, 23] ? 18.0 ? 18.0 ns write cycle [25, 26] t wc write cycle time 45 ? 55 ? ns t sce ce 1 low and ce 2 high to write end 35 ? 40 ? ns t aw address setup to write end 35 ? 40 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup to write start 0 ? 0 ? ns t pwe we pulse width 35 ? 40 ? ns t bw ble / bhe low to write end 35 ? 40 ? ns t sd data setup to write end 25 ? 25 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe we low to high z [21, 22, 23] ? 18 ? 20 ns t lzwe we high to low z [21, 22] 10 ? 10 ? ns notes 20. test conditions for all parameters other than tri-state parame ters assume signal transition time of 1 v/ns, timing reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in figure 3 on page 6 . 21. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 22. tested initially and after any design or process changes that may affect these parameters. 23. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedance state. 24. these parameters are guaranteed by design and are not tested. 25. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , bhe or ble or both = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must refer to the edge of the signal that terminates the write 26. the minimum write cycle pulse width for write cycle no. 3 (we controlled, oe low) should be equal to the sum of t hzwe and t sd .
document number: 001-93628 rev. *d page 9 of 19 cy62167gn mobl ? switching waveforms figure 5. read cycle no. 1 (a ddress transition controlled) [27, 28] figure 6. read cycle no. 2 (oe controlled) [28, 29] previous data valid data out valid rc t aa t oha t rc address data i/o 50% 50% data out valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzbe t lzbe t hzce t dbe oe ce 1 address ce 2 bhe /ble data i/o v cc supply current high i cc i sb impedance notes 27. the device is contin uously selected. oe , ce 1 = v il , bhe , ble or both = v il , and ce 2 = v ih . 28. we is high for read cycle. 29. address valid before or similar to ce 1 , bhe , ble transition low and ce 2 transition high.
document number: 001-93628 rev. *d page 10 of 19 cy62167gn mobl ? figure 7. write cycle no. 1 (we controlled) [30, 31, 32] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid t bw note ce 1 address ce 2 we data i/o oe bhe /ble notes 30. the internal write time of the memo ry is defined by the overlap of we , ce 1 = v il , bhe or ble or both = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going in active. the data input setup and hold timing must refer to the edge of the signal that terminates the write. 31. data i/o is high impedance if oe = v ih . 32. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 33. during this period the i/os are in output state. do not apply input signals.
document number: 001-93628 rev. *d page 11 of 19 cy62167gn mobl ? figure 8. write cycle no. 2 (ce 1 or ce 2 controlled) [34, 35] switching waveforms (continued) t hd t sd t pwe t ha t aw t sce t wc t hzoe data in valid t bw t sa note ce 1 address ce 2 we data i/o oe bhe /ble notes 34. the internal write time of the memo ry is defined by the overlap of we , ce 1 = v il , bhe or ble or both = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going in active. the data input setup and hold timing must refer to the edge of the signal that terminates the write. 35. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 36. during this period the i/os are in output state. do not apply input signals.
document number: 001-93628 rev. *d page 12 of 19 cy62167gn mobl ? figure 9. write cycle no. 3 (we controlled, oe low) [37, 38] figure 10. write cycle no. 4 (bhe /ble controlled, oe low) [37, 38] switching waveforms (continued) data in valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note ce 1 address ce 2 we data i/o bhe /ble t hd t sd t sa t ha t aw t wc data in valid t bw t sce t pwe note ce 1 address ce 2 we data i/o bhe /ble notes 37. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 38. the minimum write cycle pulse width should be equal to the sum of t hzwe and t sd . 39. during this period the i/os are in output state. do not apply input signals.
document number: 001-93628 rev. *d page 13 of 19 cy62167gn mobl ? truth table ce 1 ce 2 we oe bhe ble inputs/outputs mode power hx [40] xxx [40] x [40] high z deselect/power-down standby (i sb ) x [40] lxxx [40] x [40] high z deselect/power-down standby (i sb ) x [40] x [40] x x h h high z deselect/power-down standby (i sb ) l h h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) l h h l h l data out (i/o 0 ?i/o 7 ); high z (i/o 8 ?i/o 15 ) read active (i cc ) lhhllhhigh z (i/o 0 ?i/o 7 ); data out (i/o 8 ?i/o 15 ) read active (i cc ) l h h h x x high z output disabled active (i cc ) l h l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) l h l x h l data in (i/o 0 ?i/o 7 ); high z (i/o 8 ?i/o 15 ) write active (i cc ) lhlxlhhigh z (i/o 0 ?i/o 7 ); data in (i/o 8 ?i/o 15 ) write active (i cc ) note 40. the ?x? (don?t care) state for the chip enables and byte enables in the truth table refer to the logic state (either high or low). intermediate voltage levels on these pins is not permitted.
document number: 001-93628 rev. *d page 14 of 19 cy62167gn mobl ? ordering code definitions ordering information speed (ns) voltage range ordering code package diagram package type operating range 55 1.65 v?2.2 v cy62167gn18-55bvxi 51-85150 48-ball vfbga (6 8 1 mm), package code: bv48 industrial cy62167gn18-55bvxit 45 2.2 v?3.6 v cy62167gn30-45bvxi 51-85150 48-ball vfbga (6 8 1 mm), package code: bv48 cy62167gn30-45bvxit cy62167gn30-45zxi 51-85183 48-pin tsop i (pb-free) cy62167gn30-45zxit 4.5 v?5.5 v CY62167GN-45ZXI 51-85183 48-pin tsop i (pb-free) CY62167GN-45ZXIt x = blank or t blank = bulk; t = tape and reel temperature grade: i = industrial pb-free package type: xx = bv or z bv = 48-ball vfbga; z = 48-pin tsop i speed grade: xx = 55 ns or 45 ns voltage range: xx = 18 or 30 or blank 18 = 1.8 v typ; 30 = 3 v typ; blank = 5 v typ n = no ecc feature process technology: g = 65 nm bus width: 7 = 16 density: 6 = 16-mbit family code: 621 = mobl sram family company id: cy = cypress cy xx xx 621 6 7 g x xx i - n x
document number: 001-93628 rev. *d page 15 of 19 cy62167gn mobl ? package diagrams figure 11. 48-ball vfbga (6 8 1.0 mm) package outline, 51-85150 51-85150 *h
document number: 001-93628 rev. *d page 16 of 19 cy62167gn mobl ? figure 12. 48-pin tsop i (12 18.4 1.0 mm) package outline, 51-85183 package diagrams (continued) 4 5 see detail a see detail b standard pin out (top view) reverse pin out (t op view) 3 2x (n/2 tips) b b n/2 0.20 d d1 a 1 2 5 e a n/2 +1 2x 2x b n 0.10 0.10 seating plane c a1 e 9 2x (n/2 tips) 0.10 c a2 detail a 0.08mm m c a-b section b-b 7 c b1 seating plane parallel to b 6 0 detail b base metal e/2 x = a or b x gauge plan e 0.25 basic with plating 7 l c r (c) 8 c1 1 n n/2 n/2 +1 3. pin 1 identifier for revers e pin out (die down): ink or laser mark. 4. to be determined at the seating plane -c- . the seating plane is leads are allowed to rest freely on a flat horizontal surface. 5. dimensions d1 and e do not include mold protrusion. allowable 6. dimension b does not include dambar protrusion. allowable dambar material condition. dambar cannot be located on lower radius or 7. these dimensions apply to the flat section of the lead between 8. lead coplanarity shall be within 0.10mm as measured from the 9. dimension "e" is measured at the centerline of the leads. notes: 1. dimensions are in millimeters (mm). 2. pin 1 identifier for standard pin out (die up). 1.05 1.00 0.95 a2 n r 0 l e c d1 e d b c1 b1 0.50 basic 0.60 0 0.08 0.50 48 0.20 8 0.70 0.22 0.20 20.00 basic 18.40 basic 12.00 basic 0.10 0.17 0.10 0.17 0.21 0.27 0.16 0.23 a1 a 0.05 0.15 1.20 symbol min. max. dimensions nom. defined as the plane of contact that is made when the package mold protrusion on e is 0.15mm per side and on d1 is 0.25mm per side. protrusion shall be 0.08mm total in excess of b dimension at max. the foot. minimum space between protrusion and an adjacent lead to be 0.07mm . 0.10mm and 0.25mm from the lead tip. seating plane. 10. jedec specification no. ref: mo-142(d)dd. 51-85183 *f
document number: 001-93628 rev. *d page 17 of 19 cy62167gn mobl ? acronyms document conventions units of measure acronym description bhe byte high enable ble byte low enable ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory tsop thin small outline package vfbga very fine-pitch ball grid array we write enable symbol unit of measure c degree celsius mhz megahertz ? a microampere ? s microsecond ma milliampere mm millimeter ns nanosecond ? ohm % percent pf picofarad v volt w watt
document number: 001-93628 rev. *d page 18 of 19 cy62167gn mobl ? document history page document title: cy62167gn mobl ? , 16-mbit (1m 16/2m 8) static ram document number: 001-93628 rev. ecn no. orig. of change submission date description of change *b 5210733 nile 07/04/2016 changed stat us from preliminary to final. *c 5420388 vini 09/08/2016 updated electrical characteristics : changed minimum value of v oh parameter corresponding to test condition ?2.7 < v cc < 3.6, i oh = ?1.0 ma? from 2.2 v to 2.4 v. changed minimum value of v ih parameter corresponding to test condition ?2.2 < v cc < 2.7? from 2 v to 1.8 v. updated note 5 (replaced 2 ns with 20 ns). updated note 6 (replaced 2 ns with 20 ns). updated ordering information : updated part numbers. added tape and reel parts. updated to new template. *d 5783985 nile 06/23/2017 updated data retention characteristics : changed typical value of i ccdr parameter corresponding to condition ?1.2 v < v cc < 2.2 v? from 5.5 ? a to 7.0 ? a. changed maximum value of i ccdr parameter correspon ding to condition ?1.2 v < v cc < 2.2 v? from 16.0 ? a to 26.0 ? a. updated package diagrams : spec 51-85183 ? changed revision from *d to *f. updated to new template.
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